The disclosure relates generally to integrated circuit devices and associated fabrication techniques, and more specifically to a semiconductor device with a stacked gate structure and associated fabrication method.
Semiconductor structures or devices are typically embodied as one or more metal-oxide-semiconductor field effect transistors (MOSFETs) comprising an integrated circuit (IC or chip). A recent innovation in MOSFET design is the so-called FinFET, in which a thin silicon fin on top of the substrate forms the channel, with gates on either side of the fin, as shown in FIG. 1. Each fin 110 is surrounded by a gate 120 in three directions: one on each side and one on top. Tight fin pitch, taller fin height, and thinner fin width can deliver performance improvements and area scaling. However, fabrication challenges and lack of further scaling improvement for FinFETs have pushed the industry toward new architectures.
As ICs are being scaled to smaller dimensions, stacked nanosheet FETs have been developed to increase effective channel width (Weff) within a given footprint. FIG. 2 depicts the basic schema of nanosheets as gate all around FETs. Conceptually, nanosheets can be thought of as FinFETs turned on their side. This arrangement allows additional channels (sheets) to be added within the same footprint, thereby improving scaling. As depicted in FIG. 2, in stacked nanosheets, each sheet 210 is surrounded by a gate 220 on all sides, i.e. gate all around (GAA). The sheet-to-sheet gap is optimized to reduce parasitic capacitance.
Stacked Si nanowires/nanosheets are touted for advanced nodes and beyond due to enhanced scalability over FinFETs and compatibility with the VLSI (very large scale integration) approaches. Common methods to make GAA stacked requires an inner spacer to reduce gate-to-S/D epitaxial parasitics, which makes them non-self-aligned and asymmetric.
FIG. 3 illustrates a stacked gate structure in accordance with prior art methods of manufacture. In this example, the gate structure 300 comprises multiple silicon channels 302 formed over a silicon (Si) substrate 301. An epitaxial source/drain 310 is formed along the side of the gate stack (another, not shown, is also formed along the opposite side of the stack). Between the Si channels 302 are inner spacers 330 that are used during formation of the gate stack.
Typically with prior art methods, the dummy gate is removed before the nanosheets are released. As a result, half-moon shaped spacers 320 are formed when removing the sacrificial silicon germanium (SiGe) (not shown) between the Si channels 302, leading to increased gate-source/drain (S/D) fringe capacitance and potential short. This half-moon shape creates a breach 321 between the spacer and the Si channel. This breach 321 is a weak point at the corner that creates a possible leakage path between the gate to the S/D 310.